1. Field of the Invention
The present invention relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to pad structures and methods of forming the pad structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chipsets. In order to achieve high-integration and high-speed goals, dimensions of semiconductor integrated circuits continue to shrink. Various materials and techniques have been proposed to achieve these integration and speed goals and to overcome manufacturing obstacles associated therewith. In order to reduce die size, pads are formed on a region under which active or functional devices or circuits are formed, instead limited to peripheral regions of the die.
Generally, a chip having a pad formed thereover will be subjected to an electrical test during a probing step. The probing step uses a probe touching or contacting the pad for collecting electrical characteristics of devices or circuits coupled to the pad. If the electrical characteristics of devices or circuits exhibit predefined acceptance values, the chip is packaged for assembling with another substrate, such as a printed circuit board (PCB), through wire bonds. Each of the wire bonds is bonded over a respective pad. Accordingly, a pad thus is subjected to a probing force and a bonding force during the probing step and the bonding step, respectively.
If a pad dimension is reduced, the wire bond may be bonded over a region of the pad that is damaged by a probe. The contact between the pad and the wire bond is subjected to subsequent tests, such as a reliability test. In addition, the same region of the pad subjected to both a probing test and a bonding step may not tolerate the combined forces thereof. Accordingly, a “circuit under pad (CUP)” structure which includes a probing region and a bonding region for separately sustaining the probing force and the bonding force has been proposed to solve the problem.
FIG. 1A is a cross-sectional view of a prior art CUP structure. In this figure, contacts 113, 123, 135 and metal layers 115, 125 and 150 are sequentially formed over the substrate 100. Dielectric layers 110, 120, 130 are sequentially formed between the substrate 100 and metal layer 115, between the metal layers 115 and 125, and between the metal layers 125 and 150, respectively. A passivation layer 160 is formed over the dielectric layer 130 and a portion of the metal layer 150. A pad layer 170 including a probing region 170b and a bonding region 170a is formed over the passivation layer 160, contacting with the metal layer 150. A passivation layer 180 is formed over the passivation layer 160, having an opening (not labeled) partially exposing the pad layer 170.
Generally, the metal layers 150 and 125 are referred to as “a top metal layer Mtop” and “a secondary top metal layer Mtop-1.” The metal layer 115 includes an active or functional circuit pattern. As shown in FIG. 1A, the metal layers 150 and 125 serve only as buffer layers which provide desired mechanical strength against the probing and bonding forces. With the buffer layers 125 and 150, the dielectric layer 120 and the routed circuit of the metal layer 115 under the pad layer 170 are less susceptible to damage during the probing step and bonding step. However, the use of the metal layer 125 as a buffer layer under the pad layer 170 reduces the routing area of the circuit pattern 126 formed at the same layer of the metal layer 125. Accordingly, the reduction in the die area is limited.
In order to solve the problem described above, another pad structure has been proposed as shown in FIG. 1B. In this figure, the passivation layer 160 extends into a region between the probing region 170b and the metal layer 150. The passivation layer 160 under the probing region 170b serves as a buffer layer for a probing step, but the metal layer 125 under the bonding region 170a still serves as a buffer layer. Accordingly, active or functional circuits 126 can be routed under the probing region 170b, and more routing area is accessible, compared with the structure shown in FIG. 1A. However, the probing step may crack the passivation layer 160 under the probing region 170b, because the passivation layer 160, i.e., an oxide layer, is less elastic than a metal layer. The cracking 175 occurring in the passivation layer 160 causes product reliability concerns at this area.
From the foregoing, improved pad structures and methods of forming the pad structures are desired.